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asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 1 - general description the AK4564 is a 16bit stereo codec with a built - in microphone - amp, headphone - amp and speaker - amp. AK4564 has new recording features, a digital equalizer for microphone inputs and a digital alc (automatic level control). the playback features also include lineout - amp, digital volume, headphone - amp and speaker - amp. the AK4564 suits a portable application with a built - in lcd and etc. the AK4564 is housed in a space - saving 48pin lqfp package. feature 1. resolution : 16bits 2. recording function: 4 - input selector (internal mic, external mic, line x 2) pre - amp digital eq/hpf/lpf digital alc (automatic level control) circuit fadein / fadeout digital hpf for offset cancellation (fc=3.7hz@fs=48khz) enable mixing of beep signal 3. playback function digital de - emphasis filter (tc = 50/15 m s, fs = 32khz, 44.1khz and 48khz) lineout - amp digital volume: 0db ~ - 65.25db, mute headphone - amp - po: 5.3mw @ 16 w (avdd = 2.8v) speaker - amp with built - in alc - btl outp ut - po: 80mw @ 8 w enable mixing of beep signal 4. power management 5. adc characteristics (lin ? adc) s/(n+d): 87db, dr=s/n: 90db 6. dac characteristics (dac ? lineout - amp) s/(n+d): 82db, dr=s/n: 88db 7. master clock: 256fs/384fs 8. sampling rate: 8khz ~ 50khz 9. a udio data interface format: msb - first, 2 ? s compliment adc, dac: 16bit msb justified, 16bit lsb justified, i 2 s 10. ta = - 20 ~ 85 c 11. power supply voltage codec, speaker - amp: 2.6 ~ 3.6v mic/headphone/lineout - amp: 2.6 ~ 5.5v 12. power supply current all power on: 30.5ma 13. package: 48pin lqfp, 0.5mm pitch 16bit codec with built - in alc and mic/hp/spk - amp ak456 4
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 2 - sdto mclk lrck bclk sdti intr extr spk mutet vcom avdd avss csn cclk cdti dvss dvdd adc dac audio i/f controller control register i/f pdn intl mic power supply pre - amp oatt rout1 beep2 lo ut1 mpwr hvcm mrf hvdd power management hpr hpl mix +2dbv extl alc1 pre - amp rin1 lin1 svss svdd mute mvdd mvss beep1 lin2 rin2 lout2 +2dbv rout2 alc2 spkp aoutp2 aoutp1 dac hpp adc mic mic eq lpf hpf figure 1 . AK4564 block diagram
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 3 - pin/function no. pin name i/o function power supply 5 svdd - speaker amp power supply pin, +3 . 0 v 6 svss - speaker amp ground pin 15 d v d d - digital power supply pin, +2.8v 16 dvss - digital ground pin 28 hvdd - headphone - amp, l ineout power supply pin, +4.5v 30 hvcm o headphone - amp, l ineout common voltage output pin, 0.5 x hvdd 31 avss - analog ground pin 32 avdd - an alog power supply pin, +2.8v 33 vcom o common voltage output pin, 0.5 x avdd 41 mvss - mic amp ground pin 42 mvdd - mic amp power supply pin, +2.8v 43 mpwr o mic power supply pin, 1.6v @ m vdd= 2.8 v, idd=3ma(max) 44 mrf o mic power supply ripple filter pi n operation clock 7 bc l k i audio serial data clock pin 8 mclk i master clock input pin 9 lrck i input/output channel clock pin 13 sdti i audio serial data input pin 14 sdto o audio serial data output pin mic block 37 preor o rch pre-amp output pin 38 prenr i rch pre-amp negative input pin 39 extr i lch external mic input pin 40 intr i rch internal mic input pin 45 intl i lch internal mic input pin 46 extl i rch external mic input pin 47 prenl i lch pre-amp negative input pin 48 preol o lch pr e-amp output pin control data interface 10 cdti i control data input pin 11 csn i chip select pin 12 cclk i control clock input pin adc block 17 lin 1 i lch line #1 input pin 19 rin1 i rch line #1 input pin 21 lin2 i lch line #2 input pin 23 r in 2 i r ch line #2 input pin dac block 18 l out 1 o l ch line #1 output pin 20 rout 1 o rch line #1 output pin 22 l out 2 o l ch line #2 output pin 24 rout 2 o rch line #2 output pin note: all digital input pins must not be left floating.
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 4 - no. pin name i/o fun ction headphone amp 26 hpl o lch headphone amp output pin 27 hpr o rch headphone amp output pin 29 mutet o headphone amp mute capacitor pin speaker amp block 1 sp0 o speaker amp positive output pin 3 sp1 o speaker amp negative output pin 34 mout o analog mixing output pin 35 min i alc2 input pin other functions 2 mute i mute pin ? l ? : normal operation, ? h ? mute 4 pdn i reset & power - down pin ? l ? : reset & power - down, ? h ? : normal operation 25 beep2 i beep signal #2 input pin 36 beep 1 i be ep signal #1 input pin note: all digital input pins must not be left floating.
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 5 - n ordering guide AK4564vq - 20 ~ +85 c 48pin lqfp (0.5mm pitch) akd4564 evaluation board for AK4564 n pin layout sp0 preol 1 mute 48 2 sp1 3 pdn 4 svdd 5 svss 6 bclk 7 mclk 8 lrck 9 cdti 10 csn prenl 47 extl 46 45 44 mpwr 43 mvdd 42 mvss 41 intr 40 extr 39 prenr 38 sdti 13 sdto 14 dvdd 15 dvss 16 lin1 17 18 rin1 19 rout1 20 lin2 21 lout2 22 rin2 23 36 35 34 33 32 31 30 29 28 27 26 beep1 min mout vcom avdd avss hvcm mutet hvdd hpr hpl AK4564 top view lout1 intl mrf preor 37 rout2 24 11 cclk 12 25 beep2
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 6 - absolute maximum rating (avss , dvss, mvss, svss= 0v ; note 1 ) parameter symbol min max units power supplies analog 1 analog 2 mic digital speaker | dvss ? avss | ( note 2 ) | mvss ? avss | ( note 2 ) | svss ? avss | ( note 2 ) avdd hvdd mvdd dvdd svdd d gnd1 d gnd2 d gnd3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - - - 6.0 6.0 6.0 6.0 6.0 0.3 0.3 0.3 v v v v v v v v input current (any pins except supplies) iin - 10 ma a nalog input voltage ( note 3 ) ( note 4 ) vina1 vina2 - 0.3 - 0.3 avdd+0.3 mvdd+0.3 v v digital input voltage ( note 5 ) vind - 0.3 dvdd+0.3 v ambien t temperature ta - 20 85 c storage temperature tstg - 65 150 c ta=85 c ( note 7 ) pd1 - 500 mw maximum power dissipation ( note 6 ) ta=70 c ( note 8 ) pd2 - 700 mw note 1 . all voltage with respect to ground. note 2 . avss, dvss, mvss and svss must be connected to the same analog ground plane. note 3 . lin1, rin1, lin2, rin2, beep1, beep2 and min pins note 4 . extl, extr, int l , intr, prenl and prenr pins note 5 . mclk, lrck, bick, sdti, pdn, csn, cclk, cdti and mute pins note 6 . wiring density is 50% or more. note 7 . headphone - a mp and speaker - amp shouldn ? t be powered up at the same time. the maximum power supply voltage of svdd is 3.3v. note 8 . headphone - amp and speaker - amp can be powered up at the same time. warning: operation at or beyond these limits ma y result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommend operating conditions (avss , dvss, mvss, svss= 0v ; note 1 ) parameter symbol min typ max units power supplies analog 1 analog 2 mic ( note 9 ) digital speaker ( note 10 ) avdd hvdd mvdd dvdd svdd 2.6 2.6 2.6 or ? avdd ? 0.1 ? 2.6 2.6 2.8 4.5 2.8 2.8 3.0 3.6 5.5 5.5 avdd 3.3 or 3.6 v v v v v note 1 . all voltage with respect to ground. note 9 . minimum value is higher value between 2.6v and ? avdd ? 0.1 ? v. note 10 . when ta (max) is 85 c , svdd (max) is 3.3v. then headphone - amp and speaker - amp shouldn ? t be pow ered up at the same time. when ta (max) is 70 c , svdd (max) is 3.6v. then headphone - amp and speaker - amp can be powered - up at the same time. * akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 7 - analog characteristics ( ta=25 c ; avdd, dvdd, mvdd=2.8v, svdd=3.0v, hvdd=4.5v; avss, dvss, mvss, svss=0v; fs=4 8k hz ; input frequency =1khz ; measurement width=20hz ~ 20khz, unless otherwise specified) parameter min typ max units pre-amp characteristics: input resistance (intl, intr, extl, extr pins) 70 100 130 k w maximum output voltage ( note 11 ) - 4.5 dbv gain +18 +2 4 +30 db load resistance ( note 12 ) 3 30 k w load capacitance ( note 13 ) 10 pf mi c power supply voltage characteristics: mpwr pin output voltage (output current = 0ma) ( note 14 ) 1.4 1.6 1.8 v maximum output current 3 ma adc analog input characteristics: alc 1 = off resolution 16 b its input resistance ( lin1, rin1, lin2, rin2 pins) 70 100 130 k w input voltage ( note 15 ) ( note 16 ) ( note 15 ) ( note 17 ) - 5.1 - 58.5 - 4.3 - 57.7 - 3.5 - 5 6.9 dbv dbv s/(n+d) ( - 0.5 dbfs) ( note 16 ) ( note 18 ) 78 75 88 85 db db dr (-60dbfs, a-weighted) ( note 16 ) ( note 17 ) 84 57 90 61 db db s/n (a-weighted) ( note 16 ) ( note 17 ) 84 57 90 61 db db interchannel isolation ( note 16 ) ( note 17 ) 80 50 100 70 db db interchannel gain mismatch ( note 16 ) ( note 17 ) 0. 5 0.5 db db note 11 . maximum output voltage is (0.6 x a vdd) vpp . note 12 . load resistance is the value of ? rf + ri ? . (refer to figure 12 ) note 13 . when the output pin drives some capacitive load, some resistor should be added in series between output pin and capacitive load. note 14 . when the output current is 0ma, the output voltage of mpwr pin is typically (mvdd ? 1.2) v a t mvdd=2.8v and typically (mvdd - 1.4) v at mvdd=4.5v. when the output current is 3ma, the output voltage of mpwr pin is typically (mvdd ? 1.5) v at mvdd=2.8v and typically (mvdd - 1.7) v at mvdd=4.5v. note 15 . input voltages are propor tional to avdd voltage. lin1, rin1, lin2, rin2 = ( 0. 62 x avdd ) vpp intl, intr, extl, extr = (0.0013 x avdd) vpp note 16 . input from lin 1, rin 1, lin2 or rin2 pins. ivol=0db . note 17 . input from intl, intr, extl or extr pins. pre - amp gain = + 23.9db, pre = ? 1 ? , ivol = +29.625db external resistor of pre - amp is ? rf = 10k w , ri = 680 w ? . (refer to figure 12 ) note 18 . input from intl, intr, extl or extr p ins. pre - amp gain = + 23.9db, pre = ? 1 ? , ivol = +0db external resistor of pre - amp is ? rf = 10k w , ri = 680 w ? . (refer to figure 12 ) * 0dbv = 1vrms = 2.83vpp
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 8 - ( continue ) parameter min typ max units dac analog output characteristics: measured via lout1/rout1 , lout2/rout2, vol=+ 6.5 db resolution 16 b its s/(n+d) (0dbfs) 76 8 2 db dr (-60dbfs , a-weighted) 82 88 db s/n (a-weighted) 82 88 db output voltage ( note 19 ) +1.2 +2 +2.8 dbv inte rchannel isolation 80 100 db interchannel gain mismatch 0.5 db load resistance 10 k w load capacitance ( note 13 ) 30 pf headphone-amp characteristics: dac hpl/hpr pin output voltage ( note 20 ) hvdd = 3v ( note 21 ) hvdd = 4.5v - 5.5 - 1.1 - 4.7 - 0.3 - 3.9 +0.5 dbv dbv s/(n+d) ( note 20 ) hvdd = 3v ( note 21 ) hvdd = 4.5v 50 50 70 66 db db output noise voltage ( a-weighted) ; hpg= ? 0 ?, hvdd =3v, r l = 32 w hpg= ? 1 ?, hvdd =4.5v, r l = 100 w - 92 - 77 - 86 - 71 db v dbv interchannel isolation; hpg= ? 0 ?, hvdd =3v, r l = 32 w hpg= ? 1 ?, hvdd =4.5v, r l = 100 w 60 60 80 80 db db interchannel gain mismatch; hpg= ? 0 ?, hvdd =3v, r l = 32 w hpg= ? 1 ?, hvdd =4.5v, r l = 100 w 0.5 0.5 db db load resistance; hvdd=2.6 ~ 3.6v, hpg = ? 0 ? hvdd=4.0 ~ 5.5v, hpg = ? 1 ? 22 100 w w load capacitance (c1 in figure 2 ) (c2 in figure 2 ) 3 0 6.8 pf nf speaker-amp characteristics: r l = 8 w , btl, min sp0/sp1, alc2 = off output voltage ( - 6.5dbv input) - 4 - 2 0 dbv s/(n+d) ( - 2dbv output ) 30 60 db s/n (a-weighted) 81 8 9 db load resistance 8 w load capacitance 10 pf note 19 . output voltages are proportional to avdd volt age. lout1, rout1, lout2, rout2 = (1.27 x avdd ) vpp @vol = +6.5db note 20 . when dac = 0dbfs output, oatt = 0db, hpg = ? 0 ? , r l = 32 w , the output voltage is (0.59 x avdd) vpp. note 21 . when dac = - 12dbfs output, oatt = 0db , hpg = ? 1 ? , r l = 100 w , t he output voltage is (0. 98 x avdd) vpp. + - + hp - amp 16 w 16 w 0.1 m hpl, hpr c1 c2 10 w oscillation prevention circuit figure 2 . headphone - amp output circuit * 0dbv = 1vrms = 2.83vpp
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 9 - ( continue ) parameter min typ max units monaural input: (m in pin) maximum input voltage ( note 22 ) - 4 .5 dbv input resistance 14 23 33 k w monaural output : dac mix mout pin output voltage ( note 23 ) - 5.3 - 4 .5 - 3.7 dbv load resistance 10 k w load capacit ance ( note 13 ) 30 pf beep1 input: beep1 pin maximum output voltage of internal amplifier ( note 24 ) - 4.5 dbv feed - back resistance 14 20 26 k w beep 2 input: beep 2 pin maximum output voltage of inter nal amplifier ( note 24 ) - 4.5 dbv feed - back resistance 14 20 26 k w power supply current power up (pdn = ?h? ) all circuit power - up : (mic=adc=dac=vcom=hpp=spkp=aoutp 1=aoutp2 = ?1?) avdd+dvdd 13 19.5 ma mvdd ( note 25 ) 4.5 6.8 ma hvdd: hp - amp normal operation ( a out p2,1 = ?1?, hp - amp no output ) 6.5 9.8 ma svdd: spk - amp normal operation (spps= ?1?, spk - amp no output ) 6.5 9.8 ma adc: (adc=vcom= ? 1?) ( note 26 ) avdd+dvdd 7.5 - ma dac+lineout: (dac= a outp 1=aoutp2 =vcom= ?1?) avdd+dvdd 5.5 - ma hvdd: lineout normal operation, hp - amp power off ( a out 1,2 = ?1?, hpp = ? 0 ? ) 2.5 - ma powe r down (pdn = ?l? ) avdd+dvdd+hvdd+mvdd+svdd ( note 27 ) 200 m a note 22 . maximum input voltage is proportional to avdd voltage. (0.6 x avdd) vpp note 23 . dac 0dbfs out put (both l/r channels and the same phase) and oatt = 0db. note 24 . maximum output voltage is proportional to avdd voltage. (0.6 x avdd) vpp note 25 . mpwr pin supplies 0ma. note 26 . as vc om bit = ?1?, power supply current of hvdd is 0.8 ma ( typ .). note 27 . in power - down, all digital input pins including clock ( mclk, bclk and lrck ) pins are held at ? d v d d? or ?d vss ?. pdn pin is held at ?d vss ?. * 0dbv = 1vrms = 2.83vpp
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 10 - filter characteristics ( ta= 25 c ; avdd , dvdd , svdd = 2.6 ~ 3.6 v , mvdd, hvdd=2.6 ~ 5.5 v ; fs=4 8k hz ; de - emphasis = off, digital eq/hpf/lpf = off) parameter symbol min typ max units adc digital filter (lpf) : passband ( note 28 ) 0 .1db - 1.0db - 3.0db pb 0 - - 21.8 23.0 18.9 - - khz khz khz stopband ( note 28 ) sb 29.4 khz passband ripple pr 0.1 db stopband attenuation sa 65 db group delay ( note 29 ) gd - 19.0 - 1/fs gro up delay distortion d gd 0 m s adc digital filter (hpf) : frequency response ( note 28 ) - 3.0db - 0.56db - 0.15db fr - - - 3.7 10 20 - - - hz hz hz dac digital filter : passband ( note 28 ) 0.1db - 6.0d b pb 0 - 24.0 21.7 - khz khz stopband ( note 28 ) sb 26.2 khz passband ripple pr 0.06 db stopband attenuation sa 43 db group delay ( note 29 ) gd - 15.8 - 1/fs dac digital filter + analog filter : ( note 30 ) frequency response 0 ~ 20.0khz fr 0.5 db note 28 . the passband and stopband frequencies scale with fs ( system sampling rate ) . for example, adc is pb=0.45 4*fs ( @-1.0db ) , dac is pb=0.454*fs ( @-0.1db ) . note 29 . the calculated delay time caused by digital filtering. this time is from the input of an analog signal to setting the 16bit data of both channels to the output register of the ad c and includes the group delay of the hpf. for dac, this time is from setting the 16bit data of both channels on input register to the output of analog signal. note 30 . dac lout1/rout1, lout2/rout2
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 11 - dc characteristics ( ta= 25 c ; avdd, dvdd, svdd=2.6 ~ 3.6 v , mvdd, hvdd=2.6 ~ 5.5 v ) parameter symbol min typ m ax units high - level input voltage low - level input voltage vih vil 1.5 - - - - 0.6 v v high - level output voltage iout= - 200 m a low - level output voltage iout=200 m a voh vo l dvdd - 0.2 - - - - 0. 2 v v input leakage current iin - - 10 m a switching chracteristics ( ta= 25 c ; avdd, dvdd, svdd = 2.6 ~ 3.6 v , mvdd, hvdd=2.6 ~ 5.5 v; c l =2 0pf ) parameter symbol min t yp max units master clock timing (mclk) 256fs: frequency pulse width low pulse width high 384fs: frequency pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh 2.048 28 28 3.072 23 23 12.288 18.432 12.8 19.2 mhz ns ns mhz ns ns lrck timing frequency duty cycle fs duty 8 45 48 50 50 55 khz % audio interface timing bclk period bclk pulse width low pulse width high lrck edge to bclk ? - ? ( note 31 ) bclk ? - ? to lrck edge ( note 31 ) lrck to sdto (msb) delay time bclk ? ? to sdto delay time sdti latch hold time sdti latch set up time tblk tblkl tblkh tlrb tblr tlrm tbsd tsdh tsds 312.5 130 130 50 50 50 50 80 80 ns ns ns ns ns ns ns ns ns control interface timing cclk period cclk pulse width low pulse w idth high cdti latch set up time cdti latch hold time csn ? h ? time csn ? ? to cclk ? - ? cclk ? - ? to csn ? - ? tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 50 50 150 50 50 ns ns ns ns ns ns ns ns reset timing pdn pulse width pdn ? - ? to sdto delay time tpdw tpdv 150 4128 n s 1/fs note 31 . bclk rising edge must not occur at the same time as lrck edge.
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 12 - n timing diagram 1/fclk tclkl 1.5v tclkh mclk 0.6v 1/fs 1.5v lrck 0.6v tblk tblkl 1.5v tblkh bclk 0.6v figure 3 . clock timing tlrb lrck 1.5v bclk 0.6v tlrm 50%dvdd sdto tbsd 1.5v 0.6v tblr tsds 1.5v sdti 0.6v tsdh d15 (msb) d14 d0 (lsb) figure 4 . audio data input/output timing (audio i/f format: no. 0)
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 13 - csn cclk cdti tcss tcckl tcckh tcds tcdh op2 0 op1 op0 a4 1.5v 0.6v 1.5v 0.6v 1.5v 0.6v figure 5 . write command input timing csn cclk cdti tcsw tcsh d3 d2 d1 d0 1.5v 0.6v 1.5v 0.6v 1.5v 0.6v figure 6 . write data input timing 0.6v pdn tpdw tpdv sdto 50%dvdd figure 7 . reset timing
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 14 - operation overview n system clock the clocks required to operate are mclk ( 256fs/384fs), lrck ( fs) and bclk ( 32fs ~ ). the mast er clock (mclk) should be synchronized with lrck. the phase between these clocks does not matter. the frequency of mclk can be input as 256fs or 384fs. when the 384fs is input, the internal master clock is divided into 2/3 automatically. *fs is sampling fr equency . when the synchronization is out of phase by changing the clock frequencies during normal operation, the ak456 4 may occur click noise. dac input data should be ? 0 ? to avoid click noise . all external clocks ( mclk, bclk and lrck ) should always be present except mic = adc = dac = vcom = hpp = spkp = aout1p = aout2p = ? 0 ? or pdn = ? l ?. if these clocks are not provided, the ak456 4 may draw excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers . if the external clocks are not pre sent, the AK4564 should be placed in mic = adc = dac = vcom = hpp = spkp = aout1p = aout2p = ?0? or pdn = ? l ? . however, a dc, dac and alc2 are in power - down mode until mclk, bclk and lrck is input, even if they release a power - down mode by pdn pin or control register. (refer to the ?power managemen t mode?. ) n system reset ak456 4 should be reset once by bringing pdn pin ?l? upon power - up. after the system reset operation, the all internal registers become initial value . initializing cycle is 4128 /fs= 86 ms@fs=48khz. during initializing cycle, the ad c digital data outputs of both channels are forced to a 2's compliment, ?0?. output data of adc settles data equivalent for analog input signal after initializing cycle. this cycle is not for dac. n digital high pass filter the AK4564 has a digital high pass filter (hpf) to cancel dc - offset in adc. the cut - off frequency of the hpf is 3.7hz at fs=48khz and it is attenuated to ? 0.15db at 20hz. this cut - off frequency scales with the sampling frequency (fs).
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 15 - n audio serial interface format the sdti, sdto , bclk and lrck pins are connected to an external controller. the audio data format has four modes, msb - first and 2 ? s compliment. the data format is set by the dif1 - 0 bits. sdti is latched by ? - ? of bclk. sdto is latched by ? ?. when dif1= ?0? and dif0=?1 ?, only bclk=64fs is acceptable. no. dif1 bit dif0 bit sdto(adc) sdti(dac) bclk figure 0 0 0 msb justified lsb justified 3 32fs figure 8 reset 1 0 1 lsb justified lsb justified = 64fs figure 9 2 1 0 msb justified msb justified 3 32fs figure 10 3 1 1 i 2 s compatible i 2 s compatible 3 32fs f igure 11 table 1 . audio data format lrck bclk(32fs) sdto(o) sdti( i) 0 1 2 8 9 10 12 13 15 0 1 2 8 9 10 12 13 15 0 15 1 14 4 8 7 6 0 3 2 11 14 1 5 15 14 4 8 7 6 0 3 2 1 5 14 11 15 13 bclk(64fs) sdto(o) 0 1 2 3 14 15 17 18 31 0 1 2 14 15 17 18 31 0 15 1 14 0 15 14 1 2 1 15 sdti( i) 1 0 15 14 1 0 15 14 15:msb, 0:lsb lch data rch data don ? t care 2 1 13 don ? t care 16 0 16 3 13 3 13 13 3 figure 8 . audio data timing (no.0) lrck bclk(64fs) sdt o(o) 0 1 2 15 16 17 19 20 31 0 1 2 15 16 17 19 20 31 0 1 13 15 15 15 sdti(i) 1 15 0 13 12 1 15 0 13 12 15:msb, 0:lsb lch data rch data don ? t care don ? t care 15 15 12 4 14 14 0 1 18 14 0 12 14 13 1 18 figure 9 . audio data timing (no.1)
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 16 - lrck bclk(32fs) sdto(o) sdti( i ) 0 1 2 8 9 10 12 13 15 0 1 2 8 9 10 12 13 15 0 15 1 14 4 8 7 6 0 3 2 11 14 1 5 15 14 4 8 7 6 0 3 2 1 5 14 11 15 13 bclk(64fs) sdto(o) 0 1 2 3 14 15 17 18 31 0 1 2 14 14 15 17 18 31 0 15 1 14 0 15 14 14 2 1 15 sdti( i) 15:msb, 0:lsb lch data rch data don ? t care 2 1 13 don ? t care 16 0 16 3 13 13 15 14 2 1 13 0 15 14 14 2 1 0 13 15 figure 10 . audio data timing (no.2) lrck bclk(32fs) sdto(o) sdti( i ) 0 1 2 4 9 10 12 13 15 0 1 2 4 9 10 12 13 15 0 0 1 15 5 13 7 7 1 4 3 11 14 2 6 0 15 5 13 7 7 1 4 3 2 6 14 11 0 13 bclk(64fs) sdto(o) 0 1 2 3 14 15 17 18 31 0 1 2 44 14 15 17 18 31 0 1 15 0 15 13 2 1 sdti( i) 15:msb, 0:lsb lch data rch data don ? t care 2 1 14 don ? t care 16 0 16 3 14 13 15 2 1 14 0 15 13 2 1 0 14 14 3 2 2 14 3 4 f igure 11 . audio data timing (no.3)
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 17 - n mic block 1. pre - amp pre - amp includes selector, internal mic or external mic mode can be selected by int/ext bit. the pre - amp is non - inverting amplifier and internally biased to vcom volta ge with 100k w (typ.). gain (1+rf/ri) of the pre - amp is adjusted by external resistors and should be a range of +18 ~ +30db. an external capacitor is needed to cancel dc gain. the cut - off frequency is determined by an external resistor (ri) and a capacitor (c1). a capacitor of 100pf (c2) should be connected to prevent oscillation of pre - amp. pre - amp int - + rf ri + c1 ext 100pf(c2) figure 12 . pre-am p 2 . power supply for mic the power supply for microphone device is supplied from mpwr pin. mpwr pin can supply the current up to 3ma. when the output current is 0ma, the output voltage is typically (mvdd ? 1.2) v at mvdd=2.8v and typically (mvdd ? 1.4) v at mvdd=4.5v. when the output current is 3ma, the output voltage is typically (mvdd ? 1.5) v at mvdd=2.8v and typically (mvdd ? 1.7) v at mvdd=4.5v. when mic bit is ? 0 ? , the output current is not supplied.
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 18 - n analog mixing circuit for recording block lin1 (rin1) - + typ.100k w to adc 6.2k w 6.2k w typ.100k w 6.2k w 6.2k w beep1 typ.100k w beep1 ain1 ain2 - + from pre - amp pre ain1, ain2 or beep1 ri l in2 (rin2) mix1 mix2 to hp - amp - + typ.20k w typ.100k w beep1amp to rch mix1 figure 13 . analog mixing circuit for rec ording block 1. beep1 input when beep1 bit is ? 1 ? , the input signal via beep1 pin can be applied to adc. this signal level can be adjusted by an external resistor (ri). feed - back resistor of beep1 - amp is 20k 30% w . (refer to figure 13 ) 2. line input input resistance of lin1, rin1, lin2 and rin2 are typically 100k w and centered around the vcom voltage. when the input voltage exceeds +2dbv, the input signals should be attenuated down to ? 4.3dbv at va=2.8v by ext ernal resistor divider. when ain1 bit is ? 1 ? , lin1 and rin1 pins are selected. when ain2 bit is ? 1 ? , lin2 and rin2 pins are selected. if ain1 and ain2 bits are selected at the both input signals are mixed by the ratio of ? 1:1 ? 3. mix1 - amp mix1 - amp is p owered - up when adc bit = ? 1 ? or mix1p bit = ? 0 ? . 4. mix2 - amp mix2 - amp mixes pre - amp output and mix1 - amp output at the ratio of ? 1:1 ? .
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 19 - 5. polarity input signals from intl/intr, extl/extr and beep1 pins are inverted and are output from adc. input sig nals from lin1/rin1 and lin2/rin2 pins are non - inverted and output from adc. signal path polarity intl/intr adc inverted extl/extr adc inverted beep1 adc i nverted lin1/rin1 adc non - inverted lin2/rin2 adc non - inverted table 2 . polarity of recording block 6. mono mode when mono bit is ? 1 ? , the recording blocks in the AK4564 becomes mono mode. the pre - amp, mix1 - amp, mix2 - amp and adc analog block of the right channel are powered - down . and the right channel data of adc is the same as the left channel data of adc. when changing mono mode, the adc should be powered - up by changing adc bit = ? 1 ? after mono bit is changed to ? 1 ? . because click noise may occur when mono bit is changed during adc normal operation. n beep2 inp ut when beep2h bit is ? 1 ? , the input signal from beep2 pin is output to headphone - amp. when beep2s bit is ? 1 ? , the input signal from beep2 pin is output to speaker - amp. this signal level can be adjusted by an external resistor (ri). an internal resistor value (rf) is 20k 30% w . in speaker - amp, the signal level is gained to +4.6db internally. beep2 - + rf = 20k w ri figure 14 . block diagram of beep2 inputs n mute function when mute pin is ? h ? , the output signals of lineo ut, headphone and speaker - amp are muted, and become vcom or hvcm voltage. the switches of aout1, aout2, hpdac, hpmix, beep2h, alcs and beep2s become ? off ? at the same time.
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 20 - n output digital volume (oatt) attenuation range of the output digital volume is 0db to - 65.25db with mute, and the step width is 0.75db. when zec bit is ? 1 ? , the attenuation level is changed by zero crossing detection or zero crossing timeout operation. zero crossing timeout period is set by tm1 - 0 bits and fstm bit. when zce is ? 0 ? , it is changed immediately without zero crossing detection. channel independent zero crossing detection is used. if new value is written to the oatt register before oatt changes by zero crossing or timeout, the previous value becomes invalid. when the oatt register is written continually , it should take an interval of zero crossing timeout and over. n lineout lineout signals are output from lout1/rout1 and lout2/rout2 pins. the output gain is set by vol1 and vol2 bits. the common voltage of these outputs is hvcm voltage and load resistance is min. 10k w . the power supply voltage for lineout - amp is supplied from hvdd pin. the output level of lineout is constant regardless of hvdd voltage. when the voltage of hvdd pin is low, the distortion of lineout degrade s. when lineouts are muted by aout1 or aout2 bit, the outputs become hvcm voltage and the amps go to power - save - mode. when aoutp1 (aoutp2) bit is ? 0 ? , lineout - amps become power - down - mode and the output signal goes to hi - z. when pdn pin changes from ? l ? to ? h ? after power - up, lineout - amps become power - save - mode. in power - save - mode, lout1/rout1 (lout2/rout2) pins gradually become hvcm voltage via an internal resistor ( typ.200k w ) from hi - z to decrease a pop noise. when power off, the pop noise can be decrea sed by using power - save - mode.
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 21 - n headphone - amps the power supply voltage for headphone - amp is supplied from hvdd pin and centered around hvcm voltage. the load resistance and output voltage are specified by hvdd voltage. the output voltage can be change d by supplying avdd voltage and hpg bit. (refer to table 3 ) hvdd 2.6 ~ 3.6v 4.0 ~ 5.5v hpg bit 0 1 output voltage (0.59 x avdd) vpp (0.98 x avdd) vpp load resistance (min) 22 w 100 w table 3 . load resistance and output voltage of headphone - amp when hpg bit is ? 0 ? , the signals from mix1, dac and beep2 are output from headphone - amps with 0db gain. when hpg is ? 1 ? , the signals from mix1, dac and beep2 output from headphone - amps with +16.5db gain. (refer to figure 15 ) when hpdac, hpmix and beep2h bits are ? 0 ? , the input signals to headphone - amp are disabled and hpl/hpr pins output hvcm voltage. hpmix, hpdac and beep2h bits control on/off of each inp ut signal. when these bits are ? 1 ? at the same time, all input signals are mixed by the ration of ? 1:1 ? . (refer to figure 13 and figure 16 ) 0dbv - 10dbv - 20dbv - 30dbv oatt+dac hp - amp (+16.5db) fs fs - 12db - 27dbv - 15dbv +1.5dbv 0dbv - 4.5dbv - 16.5dbv oatt= - 10.5db - 4.5dbv - 16.5db v +10dbv - 10.5dbv +12dbv oatt = 0db figure 15 . headphone - amp level diagram (avdd=2.8v, hvdd=4.5v, hpg = ? 1 ? , oatt = 0db& - 10.5db) * fs = full scale
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 22 - headphone - amps are powered - up/down by hpp bit. when hpp bit is ? 0 ? , headphone - amps are powered - down and hpl and hpr pins are fixed to ? l ? (avss). at pow er - up/down, the common voltage of hpl/hpr pin is settled by a constant which determined by the internal resistor and the external capacitors. the internal resistor is 50k w (typ) at power - up, and 1k w (typ) at power - down. (refer to figure 16 ) rising time of headphone - amp: t 1 = 50k w x c1 falling time of headphone - amp: t 2= 1k w x (c1 + 2 x c2) for example; c1 = 4.7 m f, c2 = 100 m f t 1 = 235ms t 2 = 205ms + - + hp-amp 16 w 16 w c2 hpl, hpr mutet + c1 hpmix bit hpdac bit beep2h bit from mix1 from dac from beep2 figure 16 . headphone - amp internal equivalent circuit hpp bit hpdac, hpmix or beep2h bit hpl/hpr pin (1) (2) (4) (3) t 1 t 2 figure 17 . headphone - amp power - up/down timing (1) power - up headphone - amps: wr (hpp= ? 1 ? ) the common voltage of hpl/hpr pins rises by the time constant . ( t 1) (2) enable headphone - amp inputs: wr (hpdac, hpmix or beep2h = ? 1 ? ) the input signals from mix1, dac and beep2 are output. headphone - amps can output the signals while the common voltage is rising. (3) disable headphone - amp inputs: wr (hpdac=hpmix=beep 2h= ? 0 ? ) the input signal from mix1, dac and beep2 are muted. headphone - amps output hvcm voltage during muting. (4) power - down headphone - amps: wr (hpp= ? 0 ? ) the common voltage of hpl/hpr pins falls by the time constant. ( t 2)
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 23 - headphone - amps of the AK4564 h as a possibility of oscillation depending on headphone characteristics. therefore, headphone - amp oscillation prevention circuit may be needed. headphone - amps oscillation prevention circuit example is shown in figure 18 . + - + hp - amp 16 w 16 w 0.1 m hpl, hpr 10 w oscillation prevention circuit headphone figure 18 . headphone - amp oscillation prevention circuit example * when headphone - amp and speaker - amp are powered - up at the same time, refer to the condition of ? note 7 ? , ? note 8 ? and ? note 10 ? .
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 24 - n speaker block the output signal from dac is converted into a mon o signal , [ ( l+r)/2] , and is supplied to speaker - amp via alc2 c ircuit. this speaker - amp has a monaural output by btl, which can be output up to 80mw at 8 w . speaker blocks (mout, alc2 and speaker - amp) can be powered - up/down by spkp bit. when spkp bit is ? 0 ? , mout, sp0 and sp1 pins go hi - z. when spps bit is ? 0 ? and spkp bit is ? 1 ? , speaker - amp becomes power - save - mode. then sp0 pin goes hi - z and sp1 pin is output to svdd/2 via 100k w (typ. ). when pdn pin changes from ? l ? to ? h ? after power - up, speaker - amp goes to power - save - mode. in power - save - mode, sp1 pin gradually bec ome hvcm voltage via an internal resistor ( typ.200k w ) from hi - z to decrease a pop noise. when power - down (spkp = ? 0 ? ), the pop noise can be decreased by controlling via power - save - mode. * when headphone - amp and speaker - amp are powered - up at the same time, refer to the condition of ? note 7 ? , ? note 8 ? and ? note 10 ? . 1. mo no output mout pin outputs analog mixed signal, [ ( l+r)/2] of d ac output. when mout bit is ? 0 ? , this output is disabled and mout pin goes to vcom voltage. the load impedance is 10k w (min.). when spkp bit is ? 0 ? , mout pin becomes power - down - mode and outputs hi - z. 2. alc2 the input resistance of alc2 is 23k w (typ.) an d centered around vcom voltage. the level diagram of alc2 operation is shown in figure 19 alc2 limiter detection level is ? 6.5dbv regardless of power supply voltage. when the input signal level exceeds ? 6.5dbv (=fs - 2db@avdd=2.8v) , the output level of alc2 is limited. when the signal over ? 6.5dbv and is input continuously to the alc2 circuit, the changing period of alc2 limiter operation is 2/fs=42 m s@fs=48khz and the output level is attenuated by 0.5db/step. the alc2 recovery oper ation is done by zero crossing detection and the output is gained by 1db/step. the alc2 recovery operation is done until the output level of speaker - amp goes to ? 8.5dbv (=fs-4db@ avdd =2.8v) . the alc2 recovery operation period is fixed to 2048/fs=42.7ms@fs=48 khz . when inputting signal between ? 6.5dbv and ? 8.5dbv, both the limiter and recovery operations of alc2 are not done. when pdn pin changes from ? l ? to ? h ? or spkp bit changes from ? 0 ? to ? 1 ? , the initilizing cycle (2048/fs = 42.7ms @fs=48khz) starts. alc 2 is disabled during initilizing cycle, alc2 starts after finishing the initilizing cycle. parameter alc 2 limiter operation alc2 recovery operation operation start level - 6 .5dbv - 8 .5dbv fs=48khz 2/fs = 42 m s 2048/fs = 42.7ms period fs=32khz 2/fs = 63 m s 2048/fs = 64ms zero crossing detection no yes( timeout = 2048/fs ) att/gain 0.5db step 1db step table 4 . con tent of alc2
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 25 - 0dbv - 10dbv - 20dbv - 30dbv alc2 oatt+dac spk - amp fs fs - 12db - 24.75dbv - 12.75dbv fs - 2db = - 6.5dbv - 1.9dbv - 7.9dbv +4.6db - 1.4db - 4.5dbv - 2 db - 16.5dbv +6db +9.75db +18db oatt = 0db full - differential single - ended fs - 4db = - 8.5dbv - 4.5dbv - 16.5dbv oatt = - 8.25db figure 19 . speaker - amp output level diagram (avdd = 2.8v, o att = -8 .25 db & 0db) *fs = full scale - + 8 w sp0 beep2s bit alcs bit from beep2 from alc2 - + sp1 figure 20 . speaker - amp internal equivalent circuit
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 26 - n digital eq/hpf/lpf circuits the AK4564 performs equalizing, filtering and alc (automatic level control ) by digital domain for a/d converter data. the equalizing circuit emphasizes stereo separation when using internal microphone. lpf1, lpf2 and hpf2 are iir filters of 1 st order to compensate frequency response of microphone and etc. hpf3 is iir filter of 2 nd order to cut a wind - noise. refer to the section of ? alc1 operation ? about alc1. rch lch hpf3 alc1 lpf2 hpf3 alc1 lpf2 hpf1 hpf1 rch lch + equaliz ing filtering + hpf2 hpf2 wind - noise cut mix mix lpf1 lpf1 main main sub sub figure 21 . digital eq/hpf/lpf
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 27 - n alc1 operation 1. alc1 limiter operation when the alc1 limiter is enabled and ei ther lch or rch exceed the alc1 limiter detection level (lmth1 - 0), the ivol value is attenuated by the amount defined in the alc1 limiter att step (lmat1 - 0) automatically. the operation is done at the zero crossing points of the waveform. and the timeout p eriod of the zero crossing detection is set by ztm1 - 0 bits. the ivol value is common between l/r channels . after finishing the operation for attenuation, if alc1 bit is set to ? 0 ? , the operation of attenuation repeats when the input signal level exceed th e alc1 limiter detection level (lmth1 - 0). 2. alc1 recovery operation after completing an alc1 limiter operation, the alc1 recovery operation waits a time defined in wtm1 - 0 bits. if the input signal does not exceed the ? alc1 recovery waiting counter reset level (lmth1 - 0) ? during the waiting time, the alc1 recovery operation starts. the ivol value increases automatically up to the set reference level (ref7 - 0 bits) during this operation. the ivol value is common between l/r channels. the alc1 recovery operat ion is done at a period set by wtm1 - 0 bits. if the zero crossing operation of both l/r channels is completed during wtm1 - 0 period, the alc1 recovery operation waits wtm1 - 0 period and then the next recovery operation starts. when ? alc1 recovery waiting cou nter reset level (lmth1 - 0) output signal < alc1 limiter detection level (lmth1 - 0) ? during the alc1 recovery operation, the waiting timer of alc1 recovery operation is reset. when ? alc1 recovery waiting counter reset level (lmth 1 - 0 ) > output signal ? , the waiting timer of alc1 recovery operation starts. when large noise is input to microphone instantaneously, the quality of small level in the large noise can be improved by fr bit = ? 1 ? . n writing to ivol register when alc1 is off when writing control re gister continuously, the change of ivol should be written after zero crossing timeout. if ivol is changed by writing to control register before zero crossing detection, ivol value of l/r channels may not give a difference level.
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 28 - the following registers should not be changed during the alc1 operation. wtm1 - 0, ztm1 - 0, lmth1 - 0, lmat1 - 0, rgain1 - 0, ref7 - 0, fr manual mode wr (power management control & signal select registers) wr (lmat1 - 0, rgain1 - 0, lmth1 - 0) wr (ref7 - 0) alc1 operation wr (alc1= ? 1 ? ) wr (ivol7 - 0) wr (ztm1 - 0, wtm1 - 0) wr (alc1= ? 0 ? ) fi nish alc1 mode and return to manual mode finish alc1 mode? *1: the value of ivol should be the same or smaller than ref ? s yes no *2 figure 22 . registers set - up sequence at alc1 operation *2: when alc1 bit changes into ? 0 ? , it takes a period set by ztm1 - 0 bit to return manual mode.
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 29 - n fadein mode in fadein mode, the ivol value increase gradually by the step set by fdatt1 - 0 bits when fdin bit changes from ? 0 ? to ? 1 ? . the fadein period is set by fstm, ref7 - 0, fdatt1 - 0 and fdtm 1 - 0 bits. the fadein operation is done by the zero crossing detection. the operation stops when the ivol value becomes the ref value or the limiter detection level (lmth). if the limiter operation is done during fadain period, the fadein operation stops an d the alc1 operation starts. note: when fdin and fdout bits are set to ? 1 ? at the same time, fadeout operation is prior to fadein operation. sdto output alc1 bit fdin bit (1) (2) (3) (4) (5) figure 23 . example for controlling sequence in fadein oper ation (1) wr (alc1 = fdin = ? 0 ? ): the alc1 operation is disabled. to start the fadein operation, fdin bit is written in ? 0 ? . (2) wr (ivol = ? 00h ? ): ivol output is muted. the writing to ivol should wait a zero crossing timeout period set by ztm1 - 0 bits. (3) wr (alc1 = fdin = ? 1 ? ): the fadein operation starts. the ivol is fade - in from mute state. (4) the fadein operation is done until the limiter detection level (lmth1 - 0 ) or the reference level (ref7 - 0). after completing the fadein operation. the fadein operation is comple ted and the alc1 operation starts. (5) fadein time is set by ref7 - 0, fdtm1 - 0, fstm and fdatt bits e .g. ref7 - 0 = e1h(225 dec), fdtm1 - 0 = 40ms, fdatt1 - 0 = 2 step (225 x fdtm1 - 0) / fdatt1 - 0 = 225 x 40ms /2 = 4.5s
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 30 - n fadeout mode in fadeout mode, the present ivol value decreases gradually down to the mute state when fdout bit changes from ? 0 ? to ? 1 ? . the operation is done by the zero crossing detection . if the large signal is supplied to the alc1 circuit during the fadeout operation, the alc1 limi ter operation starts. however, the total time of the fadeout operation is the same time, even if the limiter operation is done. the period of fadeout is set by fstm and fdtm1 - 0 bits, the number of step is set by fdatt1 - 0 bits. when fdout bit changes into ? 0 ? during the fadeout operation, the alc1 operation starts from the present ivol value. when fdout and alc1 bits change into ? 0 ? at the same time, the fadeout operation stops and the ivol keeps the value at that time. note: when fdin and fdout bits are se t to ? 1 ? at the same time, fadeout operation is prior to fadein operation. sdto output alc1 bit fdout bit (1) (5) (6) (7) (4) (3) (2) (8) figure 24 . example for controlling sequence in fadeout operation (1) wr (fdout = ? 1 ? ): the fadeout operation starts. then alc1 b it should be always ?1? . (2) fadeout time is set by ref7 - 0, fdtm1 - 0 and fdatt bits. e .g. ref7 - 0 = e1h(225 dec), fdtm1 - 0 = 40ms, fdatt1 - 0 = 2 step (225 x fdtm1 - 0) / fdatt1 - 0 = 225 x 40ms / 2 = 4.5s (3) the fadeout operation is completed. the ivol va lue is the mute state. if fdout bit ke e p s ? 1 ? , the ivol value keeps the mute state. (4) analog and digital outputs are muted externally. then the ivol value is the mute state. (5) wr (alc1 = fdout = ? 0 ? ): exit the alc1 and fadeout operations (6) wr (ivol = xxh): the ivol value should be set to the same or smaller than ref ? s. (7) wr (alc1 = ? 1 ? , fdout = ? 0 ? ): the alc1 operation restarts. but the alc1 bit should be written until completing zero crossing detection operation of ivol. (8) release an external mute function for anal og and digital outputs.
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 31 - n control register write timing the data on the 3 wires serial interface consists of op - code (3bit), address (msb - first, 5bit) and control data (msb - first, 8bit). the transmitting data is output to each bit by ? ? of cclk, the receiving data is latched by ? - ? of cclk. writing data becomes effective by ? - ? of csn. cclk always needs 16 edges of ? - ? during csn = ? l ? . pdn pin = ? l ? resets the registers to their defalut values.only write to address 00h to 0ch. writing to the contro l registers except for op2 - 0 bit = ? 101 ? are ignored. csn cclk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cdti op2 op1 a2 a3 a1 a0 a4 d7 d6 d5 d4 d3 d2 d1 d0 op0 op2-op0: op code (101:writ e) a4-a0: register address d7-d0: control data ? 1 ? ? 0 ? ? 1 ? figure 25 . control data timing
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 32 - n register map the following registers are reset at pdn pin = ?l? . addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h signal select 1 0 hpmix hpg beep1 ain2 ain1 pre int/ext 01h signal select 2 spps alcs beep2h beep 2s a out 2 aout1 mout hp dac 02h power management control aout p2 aoutp1 spkp hpp vcom dac adc mic 03h mode control vol2 - 1 vol2 - 0 vol1 - 1 vol 1 - 0 dif 1 dif 0 d em1 dem0 04h filter select 1 mix1 mix0 hpf3 hpf2 - 1 hpf2 - 0 hpf1 - 1 hpf1 - 0 fsf 05h filter select 2 0 0 0 lpf2d lpf2 - 1 lpf2 - 0 lpf1 - 1 lpf1 - 0 06h timer select tm1 tm0 fdtm1 fdtm0 ztm1 ztm0 wtm1 wtm0 07h alc mode control 1 0 gsel fdatt1 fdatt0 rgain1 rgain0 lmat1 lmat0 08h alc mode control 2 0 fstm 0 0 0 fr lmth1 lmth0 09h alc mode control 3 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 0ah input digital volume control ivol7 ivol6 ivol5 ivol4 ivol3 ivol2 ivol1 ivol0 0bh operation mode 0 0 mix1p mono alc2 fdin fdout alc1 0ch output digital att control zce oatt6 oatt5 o att 4 o att 3 o att 2 o att 1 o att 0 table 5 . AK4564 register map signal select 1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h signal select 1 0 hpmix hpg beep1 ain2 ain1 pre int/ext default 0 0 0 0 0 0 1 0 int/ext : select internal / external mic 0: internal mic ( default ) 1: external mic pre: enable input signal from pre - amp to adc. 0: off ( default ) 1: on ain1: enable input signal from lin1/rin1 pin to adc. 0: off ( default ) 1: on ain2: enable input signal from lin2/rin2 pin to adc. 0: off ( default ) 1: on beep1: enable input signal from beep1 pin to adc. 0: off ( default ) 1: on hpg: select gain of headphone - amp 0: 0db ( default ) 1: + 16.5db hpmix: enable input signal from mix1 - a mp to headphone - amp 0: off ( default ) 1: on
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 33 - signal select 2 addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h signal select 2 spps alcs beep2h beep 2 s aout 2 aout1 mout hpdac default 0 0 0 0 0 0 0 0 hpdac: enable input signal from headphone - amp to dac out put 0: off ( default ) 1: on mout: enable mono output [ mixing = ( l+r ) /2 ]. 0: off ( default ) 1: on when mout bit = ? 0 ? , mout pin outputs vcom voltage. a out 1: enable lout1/rout1 output 0: off ( default ) 1: on when aout1 bit = ? 0 ? , the outputs become hvcm voltage and the amps go to power - save - mode. a out 2: enable lout2/rout2 output 0: off ( default ) 1: on when aout2 bit = ? 0 ? , the outputs become hvcm voltage and the amps go to power - save - mode. beep 2 s : enable beep2 to speaker - amp 0: off ( default ) 1: on beep 2h: enabl e beep2 to headphone - amp 0: off ( default ) 1: on alcs: enable alc2 to speaker - amp 0: off ( default ) 1: on spps: speaker - amp power - save - mode 0: power - save - mode (default) 1: normal operation when spps bit = ? 0 ? , sp0 pin becomes hi - z and sp1 pin is generated t o svdd/2 voltage.
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 34 - power management control addr register name d7 d6 d5 d4 d3 d2 d1 d0 0 2 h power management control aout 2 p aout1p spkp hpp vcom dac adc mic default 1 1 1 0 1 1 1 1 mic: mic block ( pre-amp and mpwr ) power control. 0: off 1 : on ( defaul t ) when mic bit = ? 0 ? , output of pre - amp is hi - z and mpwr is terminated by 5k w (typ) to mvss. adc: adc power control 0: off 1: on ( default ) when adc bit = ? 0 ? , sdto pin is fixed to ?l?. when adc bit changes from ?0? to ?1?, initializing cycle (4128 /fs= 86 ms @fs=48khz ) starts. after initializing cycle, digital data of adc is generated . dac: dac power control 0: off 1: on ( default ) vcom: commo n voltage ( vcom and hvcm ) power control 0: off 1: on ( default ) hpp: headphone - amp power control 0: off ( default ) 1: on when hpp bit = ? 0 ? , o u t put of headphone - amp becomes ?l? ( a vss) . spkp: speaker block power control ( including beep 2 , mout, alc2 and speaker - amp ) 0: off 1: on ( default ) when spkp bit = ? 0 ? , o utput of speaker - amp and mout are hi- z . aout 1 p: l out1/rout1 ? s ampli fiers power control 0: off 1: on ( default ) when aout1p bit = ? 0 ? , lout1/rout1 pins are hi - z. aout 2 p: l out2/rout2 ? s amplifiers power control 0: off 1: on ( default ) when aout2p bit = ? 0 ? , lout2/rout2 pins are hi - z. each block can be partially powered - down b y on/off ( ?1? / ?0? ) of these bits . when pdn pin goes ?l?, all circuit s are powered - down regardless of these bits. however in this case, all register are reset to the default value. when all these registers in 02h goes ? 0 ? , all circuits can be powered - dow n with keeping registers values. vcom bit must go ? 1 ? before each block operates. except the case of mic=adc=dac=vcom=hpp=spkp=aout1p=aout2p = ?0? or pdn pin = ?l?, mclk, bclk and lrck should not be stopped.
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 35 - mic mpwr mout alc2 hp aout1 vcom dac att aout2 spk adc alc1 input selector beep2 d0:mic *1 d4:hpp d5:spkp d2:dac d1:adc d3:vcom d6:aout1p d7:aout2p *1: beep2 is enabled by controlling spkp or hpp bit. hvcm *2 *2: mix1 - amp is enabled by controlling adc or dacmix bit figure 26 . power management control mic mpwr mout alc2 hp aout1 vcom hvcm dac att aout2 spk adc alc1 input selector beep2 mvdd avdd hvdd svdd avdd avdd vcom: avdd hvcm: hvdd hvdd hvdd avdd figure 27 . analog power supply source of each block
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 36 - mode control addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h mode control vol2 - 1 vol2 - 0 vol1 - 1 vol1 - 0 dif1 dif 0 dem1 dem0 defa ult 0 1 0 1 0 0 0 1 dem1-0 : select de - emphasis frequency the ak456 4 includes the digital de - emphasis filter ( tc = 50/15 m s ) by iir filter. the filter corresponds to three sampling frequencies ( 32khz, 44.1khz and 48khz ) . the de - emphasis filter selected by dem0 and dem1 registers are enabled for input audio data. dem1 dem0 mode 0 0 44.1khz 0 1 off 1 0 48khz 1 1 32khz default table 6 . de - emphasis frequencies d if 1-0 : select audio data format no. dif1 bit dif0 bit sdto(adc) sdti(dac) bclk figure 0 0 0 msb justified lsb justified 3 32fs figure 8 default 1 0 1 lsb justified lsb justified = 64fs figure 9 2 1 0 msb justified msb justified 3 32fs figure 10 3 1 1 i 2 s compatible i 2 s compatible 3 32fs f igure 11 table 7 . audio data format vol 1: lout1/rout1 output volume setting vol2: lo ut1/rout1 output volume setting the power supply voltage for lineout - amp is supplied from hvdd pin. the output level of lineout is constant regardless of hvdd voltage. when the output voltage of hvdd pin is low, the distortion of lineout degrades. vol2 - 1 vol1 - 1 vol2 - 0 vol 1 - 0 g ain avdd voltage lineout 0 0 +7.1db 2.6v +2dbv 0 1 + 6.5 db 2.8v +2dbv 1 0 +5.9db 3.0v +2dbv 1 1 0db 2.8v - 4.5dbv default table 8 . lineout volume setting
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 37 - filter select 1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 0 4 h filter select 1 mix1 mix0 hpf3 hpf2 - 1 hpf2 - 0 hpf1 - 1 hfp1 - 0 fsf default 0 0 0 0 0 0 0 0 fsf: select sampling rate to match a coefficient of digital filter 0: fs = 48khz ( default ) 1: fs = 32khz hpf1: select cut - off frequency of hpf1 in eq block. this is 1 st order and iir filter. cut - off frequency hpf1 - 1 hpf1 - 0 fs=32khz fs=48khz 0 0 off off 0 1 6khz 6khz 1 0 7.5khz 7.5khz 1 1 9khz 9khz default table 9 . select cut - off frequency of hpf1 hp f2: select cut - off frequency of hpf2 to revise frequency response. this is 1 st order and iir filter. cut - off frequency hpf2 - 1 hpf2 - 0 fs=32khz fs=48khz 0 0 off off 0 1 100hz 100hz 1 0 200hz 200hz 1 1 300hz 300hz default table 10 . select cut - off frequency of hpf2 hpf3: select cut - off frequency of hp3 for wind - noise cut. this is 2 nd order and iir filter. the cut - off frequency is fixed to 400hz and is changed by fsf bit. 0: off ( default ) 1: on mix1 - 0: select mixing val ue in eq block. when hpf1 is off, this circuit is also off. mix1 mix0 main : sub 0 0 1: 1 0 1 1: 1.25 1 0 1: 0.5 1 1 1: 0.75 default table 11 . select mixing value
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 38 - filter select 2 addr register name d7 d6 d5 d4 d3 d2 d1 d0 05 h filter select 2 0 0 0 lpf2d lpf2 - 1 lpf2 - 0 lpf1 - 1 lpf1 - 0 default 0 0 0 0 0 0 0 0 lpf1: select cut - off frequency of lpf1 to revise frequency response. this is 1 st order and iir filter. cut - off frequency lpf1 - 1 lpf1 - 0 fs=32khz fs=4 8khz 0 0 off off 0 1 6khz 6khz 1 0 9khz 9khz 1 1 13.5khz 13.5khz default table 12 . select cut - off frequency of lpf1 lpf2: select cut - off frequency of lpf2 to revise frequency response. this is 1 st order and iir filter. cut - off frequency lpf2 - 1 lp f2 - 0 fs=32khz fs=48khz 0 0 3khz 3khz 0 1 4.5khz 4.5khz 1 0 6.75khz 6.75khz 1 1 10.125khz 10.125khz default table 13 . select cut - off frequency of lpf2 lpf2d: enable lpf2 0: off ( default ) 1: lpf2 on
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 39 - timer select addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h timer select tm1 tm0 fdtm1 fdtm0 ztm1 ztm0 wtm1 wtm0 default 0 1 0 1 1 0 1 0 wtm1-0 : alc1 recovery waiting period a period of recovery operation when any limiter operation does no t occur during alc1 operation. wtm1 wtm0 alc1 recovery period 0 0 6ms 0 1 24 ms 1 0 48 ms default 1 1 96 ms table 14 . alc1 recovery operation waiting period ztm1-0 : ivol zero crossing timeout period when ivol of each l/r ch annels do zero crossing or timeout independently, the ivol value is changed by m p write operation or alc1 recovery operation. z tm1 z tm0 zero crossing timeout period 0 0 6ms 0 1 24 ms 1 0 48 ms default 1 1 96 ms table 15 . zero crossing timeout period fdtm1-0 : fadein/out cycle setting the fadein/out operation is done by a period set by fdtm1 - 0 bits when fdin or f dout bit s are set to ? 1 ? . when ivol of each l/r channel do zero crossing or timeout independently , the ivol value is changed. fdtm 1 fdtm 0 fadein/out period 0 0 20 ms 0 1 40 ms default 1 0 48 ms 1 1 56ms table 16 . fadein/out period tm1 - 0: select zero crossing timeout period of oatt these bits are enabled at zce = ? 1 ? . tm1 tm0 zero crossing timeout period 0 0 8ms 0 1 16ms default 1 0 32ms 1 1 64ms table 17 . select zero crossing timeout of oatt * wtm1 - 0, ztm1 - 0, fdtm1 - 0 and tm1 - 0 have the same time between fs=32khz (fstm bit = ? 1 ? ) and fs=48khz (fstm bit = ? 0 ? ).
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 40 - alc mode control 1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 0 7 h alc mode control 1 0 gsel fdatt1 fdatt 0 r gain1 rgain0 lmat1 lmat0 default 0 0 0 0 0 0 0 0 lmat1 - 0 : alc1 limiter att step the ivol value is attenuated when the input signal exceeds the alc1 limiter detection level. the number of step to attenuate is decided by output level. alc1limiter att step lmat1 lmat0 alc1 output 3 lmth alc1 output 3 fs alc1 output 3 fs + 6db alc1 output 3 fs + 12db 0 0 1 1 1 1 default 0 1 2 2 2 2 1 0 2 2 4 4 1 1 2 4 4 8 table 18 . alc1 limiter att step r gain1 - 0 : alc1 recovery gain step during the alc1 recovery operation, the number of steps changed from current i vol value is set. for example, when the current i vol value i s 30h, r gain 1 - 0 = ?0 1 ? are set, i vol changes to 32h by the auto limiter operation, the input signal level is gained by 0.75 db ( =0. 37 5db x 2 ) . when the i vol value exceeds the reference level ( ref 7 -0 ) , the i vol value does not increase. rgain1 r gain0 gain ste p 0 0 1 0 1 2 1 0 3 1 1 4 default table 19 . alc1 recovery gain step fdatt 1 - 0 : fadein/out att step setting during the fadein/out operation, the number of steps changed from current ivol value is set. fdatt1 fdatt0 att ste p 0 0 1 0 1 2 1 0 3 1 1 4 default table 20 . fadein/out att step setting gsel: select ivol gain 0: mic ( default ) 1: line
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 41 - alc mode control 2 addr register name d7 d6 d5 d4 d3 d2 d1 d0 0 8 h alc mode control 2 0 fstm 0 0 0 fr lmth1 lmth0 default 0 0 0 0 0 1 1 0 lmth1 - 0: alc1 limiter detection level / recovery counter reset level lmth1 lmth0 alc1 limier detection level alc1 recovery waiting counter reset level 0 0 alc1 output 3 - 2.5dbfs - 2.5dbfs > alc1 output 3 - 4.1dbfs 0 1 alc1 output 3 - 4.1dbfs - 4.1dbfs > alc1 output 3 - 6.0dbfs 1 0 alc1 output 3 - 6.0dbfs - 6.0dbfs > alc1 output 3 - 8.5dbfs 1 1 alc1 output 3 - 8.5dbfs - 8.5dbfs > alc1 output 3 - 12dbfs default table 21 . alc1 limiter detecti on level / recovery counter reset level fr: enable alc1 fast recovery operation 0: disable 1: enable ( default ) if the impulse noise is supplied, the alc1 recovery operation becomes the faster period than a set of ztm1 - 0 and wtm1 - 0 bits. fstm: this data determines the time of alc1 recovery period (wtm1 - 0 bit), ivol zero crossing timeout period (ztm1 - 0 bit), oatt zero crossing timeout period (tm1 - 0 bit) and fadein/out period (fdtm1 - 0 bit) 0: fs = 48khz ( default ) 1: fs = 32khz
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 42 - alc mode control 3 addr register name d7 d6 d5 d4 d3 d2 d1 d0 0 9 h alc mode control 3 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 default 1 1 1 0 0 0 0 1 ref 7 -0 : reference value at a lc1 recovery operation. 0.375db step, 242 levels during the alc1 recovery opera tion , if the ref value exceeds the setting reference value by gain operation, ref value does not become larger than the reference value. gsel bit selects the gain table of either mic or line. gain(db) data mic (gsel bit = ? 0 ? ) line (gsel bit = ? 1 ? ) f 1h + 36 .0 + 6 .0 f0h + 35.625 + 5.625 efh + 35.25 + 5.25 e2h + 30.375 + 0.375 e1h + 30 .0 0 default e0h + 29.625 - 0.375 dfh + 29.25 - 0.75 0 4 h - 52.875 - 82.875 0 3 h - 53.25 - 83.25 0 2 h - 53.625 - 83.625 0 1 h - 54 .0 - 84 .0 0 0h mute mute tabl e 22 . set - up reference level at alc1 recovery operation
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 43 - input digital att control addr register name d7 d6 d5 d4 d3 d2 d1 d0 0 a h input digital volume control ivol7 ivol6 ivol5 ivol4 ivol3 ivol2 ivol1 ivol0 default 1 1 1 0 0 0 0 1 ivol7 -0: input digital volume; 0.375db step, 242 level when the alc1 operation is off, ivol can be used as volume. when the ivol is changed, the ivol is detected by zero crossing. zero crossing timeout period is set by ztm1 - 0 and fstm bits. the chang e of gain table between mic and line is set by gsel bit. during the alc1 operation, the writing value in ivol7 - 0 bits is ignored gain(db) data mic (gsel bit = ? 0 ? ) line (gsel bit = ? 1 ? ) f1h + 36 .0 + 6 .0 f0h + 35.625 + 5.625 efh + 35.25 + 5.25 e2h + 30.375 + 0.375 e1h + 30 .0 0 default e0h + 29.625 - 0.375 dfh + 29.25 - 0.75 0 4 h - 52.875 - 82.875 0 3 h - 53.25 - 83.25 0 2 h - 53.625 - 83.625 0 1 h - 54 - 84 0 0h mute mute table 23 . attenuation value of input digital volume
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 44 - operation mode addr register name d7 d6 d5 d4 d3 d2 d1 d0 0 b h operation mode 0 0 mix1p mono alc2 fdin fdout alc1 default 0 0 0 0 1 0 0 0 alc1 : alc1 enable flag 0 : disable ( default ) 1 : enable fdout : fadeout enable flag 0 : d isable ( default ) 1 : e nable fdin : fadein enable flag 0 : d isable ( default ) 1 : e nable alc2 : alc2 enable flag 0 : disable 1 : enable ( default ) after initializing cycle (2048/fs=42.7ms@fs=48khz) , alc2 is enabled. this initializing cycle starts when pdn pin change ? l ? to ? h ? or spkp bit change from ? 0 ? to ? 1 ? . mono : mono mode for recoding when the microphone and line inputs are mon o, rch output data of sdto can be changed to lch data. then pre - amp, mix1 - amp, mix2 - amp and adc analog block of right channel are powered down. sdto o utput data mono lch rch mode 0 lch rch stereo default 1 lch lch mono table 24 . sdto output data mix1p: mix1 - amp power control mix1p and adc bits are ored. 0 : power off ( default ) 1 : power on
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 45 - output digital att control addr r egister name d7 d6 d5 d4 d3 d2 d1 d0 0ch output digital att contro l zce oatt6 oatt5 oatt4 o att3 o att2 o att1 o att 0 default 1 1 0 1 1 0 0 0 zce: oatt zero crossing enable flag 0: disable 1: enable ( default ) o att6 -0 : output digital volume; 89 l evel, 0db ~ - 65.25 db & mute , 0.75db step this volume includes zero crossing detection circuit. when zce is ? 1 ? , the change of volume is detected by zero crossing independently. zero crossing timeout period is set by tm1 - 0 and fstm bits. when zce is ? 0 ? , th e oatt is changed immediately . data(hex) att level 58h 0 db default 57h - 0.75 db 56h - 1.5 db 3dh - 20.25 db 3ch - 21 .0db 3bh - 21.75 db 0 3 h - 63.75 db 0 2 h - 64.5 db 0 1 h - 65.25 db 0 0 h mute table 25 . attenuation v alue of output digital volume
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 46 - system design figure 28 shows the system connection diagram. an evaluation board (akd4564) is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. preol sp0 1 2 3 4 5 6 7 8 9 11 10 mute pdn svdd svss bclk mclk lrck cdti csn min prenl extl mpwr mvdd mvss intr prenr sdti beep1 13 14 15 16 17 18 19 20 21 22 23 dvss sdto dvdd lin1 rin1 rout1 lin2 lout2 rin2 mout vcom avdd avss hv cm mutet hvdd hpr hpl AK4564 lout1 intl mrf sp1 36 35 34 33 32 31 30 29 28 26 27 48 47 46 45 44 43 42 41 40 39 38 12 cclk 24 rout2 beep2 25 preor 37 +2.6 ~ 5.5v analog supply extr + + + + + + + +2.6 ~ 3.6v analog supply +2.6 ~ 3.6v analog supply +2.6 ~ 5.5v analog supply + + dsp and m p headphone speaker 10 c1 c2 + + 2.2 m c1 c2 c1 c2 c1 1 m + c2 c1 c1 2.2 m c1: 0.1 m f c2: 10 m f c3: 0.22 m f c2 c1 + 4.7 m c3 c3 c3 c3 1k 1k c1 10 10 c1 10k 680 c2 10k 680 c2 100p 100p figure 28 . system connection diagram
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 47 - package 1 12 48 13 7.0 9.0 0.2 7.0 9.0 0.2 0.22 0. 08 48pin lqfp(unit:mm) 0.10 37 24 25 36 0.16 0. 07 1.40 0.05 0.13 0. 13 1.70max 0 ~ 10 0.10 m 0.5 0. 2 0.5 n package & lead frame material package molding compound : epoxy lead frame material : cu lead frame surface treatment: solder plate (pb free)
asahi kasei [ AK4564] ms0140 - e - 0 1 2002/0 7 - 48 - marking AK4564vq xxxxxxx 1 xxxxxxxx: d at e code identifier i m portant notice these products and their specifications ar e subject to change without notice. before considering any use or a pplication, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and r egulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or mainte nance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a cri tical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high stan dards of performance and reliability. it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditi ons, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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